1. Field of the Invention
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for compressing and storing a test program used in a test of a device under test.
2. Description of the Related Art
A test apparatus performs a test of a DUT (Device Under Test) that is an object of the test, based on a test program. The test program includes, in each instruction cycle, an instruction to be executed by the test apparatus, and a test pattern to be output to each terminal of the DUT or an expected value pattern to be compared with an output pattern output from each terminal of the DUT.
In order to reduce the data amount of the test program, a test apparatus that compresses the test program using a repeat instruction has been conventionally used. FIG. 7 shows a conventional compression format of the test program. In the test program shown in FIG. 7, NOP (no operation) instruction is executed in the first instruction cycle, so that a test pattern {0, 1, 1, 0} is output to terminals 1, 2, 3 and 4, respectively. Similarly, NOP instruction is executed in the second instruction cycle, so that a test pattern {1, 0, 1, 0} is output to the terminals 1, 2, 3 and 4, respectively. In the third instruction cycle, IDXI instruction, that is a repeat instruction, is executed, so that a test pattern {1, 1, 1, 0} is continuously output to the terminals 1, 2, 3 and 4, respectively, during 100 cycles. In this manner, in the conventional test apparatus, in a case where the same pattern is used during a plurality of instruction cycles, a repeat instruction is used so as to reduce the size of the test program.
On the other hand, with increase of operating speeds of electronic devices, a transmission rate of a signal input to and output from an electronic device dramatically increases. In order to test such an electronic device, a test apparatus is required to generate a test pattern or an expected pattern at a higher speed.
However, it is difficult to dramatically improve the performance of the test apparatus by reducing the instruction cycles in which the test program is executed. Thus, it is a realistic approach to achieve a test apparatus that generates a pattern at a high speed while executing an instruction at a relatively low speed, by supplying a plurality of test pattern or an expected pattern during one instruction cycle. In a case where compression using the repeat instruction is employed in such a testing device, compression can be performed only when the same pattern sequence that is completely the same for all terminals is continuously used during a plurality of instruction cycles. However, when even a part of the pattern sequence is different, compression cannot be applied. Thus, only by employing the compression method using the repeat instruction, compression efficiency may lower to cause shortage of a memory region for storing the test program.